Bit access problems in 2-1/2D 2-wire memories

The obvious cost advantage of a 2-wire 2-1/2D core mat over a 3-wire mat has, in the past, been offset by the increased complexity of the access and detection circuitry required for a 2-wire array. This paper will concentrate on 2-wire bit accessing schemes and describe one which appears to be cheaper and less noisy than the conventional bit access which uses a complete matrix per bit. It will then discuss the readout noise problems. To predict the amplitude of noise a multistate core model similar to J. Reese Brown's will be developed. The paper will then show how the individual core characteristics can be extrapolated to predict overall optimum memory performance.