一个高速Prolog解释器的实现

SIGPLAN Conferences and Workshops Pub Date : 1987-07-01 DOI:10.1145/29650.29663

A. Krall

{"title":"一个高速Prolog解释器的实现","authors":"A. Krall","doi":"10.1145/29650.29663","DOIUrl":null,"url":null,"abstract":"This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.","PeriodicalId":414056,"journal":{"name":"SIGPLAN Conferences and Workshops","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Implementation of a high-speed Prolog interpreter\",\"authors\":\"A. Krall\",\"doi\":\"10.1145/29650.29663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.\",\"PeriodicalId\":414056,\"journal\":{\"name\":\"SIGPLAN Conferences and Workshops\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1987-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"SIGPLAN Conferences and Workshops\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/29650.29663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"SIGPLAN Conferences and Workshops","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/29650.29663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

本文描述了在标准微处理器(16mhz MC68020上的50klips)上实现高速Prolog解释器。解释器基于直接线程代码。通过这种方法，解释程序可以获得与编译程序相同的速度，但只使用十分之一的内存。本文的第一部分介绍了解释器的实现。第二部分比较了编译器的实现、运行时和存储需求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of a high-speed Prolog interpreter

This paper describes the implementation of a high speed Prolog interpreter on a standard microprocessor (50 KLIPS on a 16 MHz MC68020). The interpreter is based on direct threaded code. By this method an interpreted program achieves the same speed as a compiled program, but uses only a tenth of memory. The first part of this paper describes the implementation of the interpreter. The second part compares the implementation, the runtime and the storage requirements with that of a compiler.

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SIGPLAN Conferences and Workshops

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