A low power receiver architecture for Near Field Communication readers

In this paper, a low power and direct-to-digital receiver architecture for Near-Field Communications (NFC) is proposed. There are several blocks used in a typical receiver part of the NFC reader; such as a mixer, an envelope detector (or a low pass filter), a Low Pass Analog-to-Digital Converter (LP-ADC), and finally a Phase-Locked-Loop (PLL). These four blocks, especially PLL and ADC, are power hungry because of over-sampling required to obtain reasonable Signal-to-Noise-Ratio (SNR) for a NFC device. The proposed receiver architecture uses a Band-Pass (BP) Delta-Sigma ADC and trimmed crystal oscillator in order to obtain direct conversion of the received NFC signal with its carrier.