6.1 40nm CMOS的56Gb/s PAM-4/NRZ收发器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI:10.1109/ISSCC.2017.7870285

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee

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引用次数: 53

摘要

超高速数据链路，如400GbE连续推送收发器，以实现更好的性能和更低的功耗。本文提出了一个56Gb/s的高度并行TRX，集成了序列化/反序列化器、FFE/CTLE/DFE、CDR和眼监测电路。在14GHz时，在24dB损耗下实现BER<10−12，功耗为602mW。

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6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<10−12 under 24dB loss at 14GHz while dissipating 602mW of power.

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2017 IEEE International Solid-State Circuits Conference (ISSCC)

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