Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications

To minimize the consumption of power, chip area and to enhance the battery life and performance of the system, the low power VLSI circuit is designed. Scaling design or counter is used as a key element for increasing or decreasing the values of an operator depending on its previous state. During the counting process frequency and time can be measured. The major problem in scaling circuit is the power consumption due to the power dissipation in the clock during standby mode. One-third of the total power is consumed by the clock signal in a counter. In this paper, power consumption is reduced by minimizing the number of switching activities. The power consumption in counter further reduced by reducing the power consumption in flip-flops. This can be achieved by combining True Single Phase Clock Logic (TSPCL) with Self-controllable Voltage Level (SVL) technique. TSPCL performs the Flip-Flop operation at high speed with low power. SVL technique suppresses the power due to leakage current and also uses less number of transistors thus the system complexity also gets reduced. The proposed design consumes 27% less power than the existing design. The proposed methodology reveals promising avenues for low power modern electronics items.