{"title":"面积有效矢量乘法IDDT测试校准","authors":"M. Itskovich","doi":"10.1109/AUTEST.2009.5314026","DOIUrl":null,"url":null,"abstract":"This paper proposes an area efficient signal processing architecture to perform Iddt test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300kHz, independently of vector size.","PeriodicalId":187421,"journal":{"name":"2009 IEEE AUTOTESTCON","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Area efficient vector multiplication for IDDT test calibration\",\"authors\":\"M. Itskovich\",\"doi\":\"10.1109/AUTEST.2009.5314026\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an area efficient signal processing architecture to perform Iddt test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300kHz, independently of vector size.\",\"PeriodicalId\":187421,\"journal\":{\"name\":\"2009 IEEE AUTOTESTCON\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE AUTOTESTCON\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AUTEST.2009.5314026\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE AUTOTESTCON","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AUTEST.2009.5314026","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Area efficient vector multiplication for IDDT test calibration
This paper proposes an area efficient signal processing architecture to perform Iddt test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300kHz, independently of vector size.
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