{"title":"一种用于微处理器内核测试和硅调试的I-IP","authors":"P. Bernardi, M. Grosso, M. Rebaudengo, M. Reorda","doi":"10.1109/MTV.2005.11","DOIUrl":null,"url":null,"abstract":"Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor software-based self test (SBST)","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores\",\"authors\":\"P. Bernardi, M. Grosso, M. Rebaudengo, M. Reorda\",\"doi\":\"10.1109/MTV.2005.11\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor software-based self test (SBST)\",\"PeriodicalId\":179953,\"journal\":{\"name\":\"2005 Sixth International Workshop on Microprocessor Test and Verification\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 Sixth International Workshop on Microprocessor Test and Verification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTV.2005.11\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Sixth International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2005.11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor software-based self test (SBST)
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