一种1000门ttl兼容主片阵列

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468738

E. Gonauser, W. Braeckelmann, K. Delker, K. Schoen, W. Wilhelm, A. Glasl

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引用次数: 0

摘要

描述了一个36.6 mm2的主片阵列，具有58个完全ttl兼容的I/ o端口。该芯片具有1ns的内部栅极延迟，每个栅极的功耗为0.6 mW，单个5v电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1000-Gate TTL-Compatible Masterslice Array

A 36.6 mm2 masterslice array with 58 fully TTL-compatible I/O-ports is described. The chip features 1ns internal gate delay, a power dissipation of 0.6 mW per gate and a single 5 V supply.

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ESSCIRC 80: 6th European Solid State Circuits Conference

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