{"title":"EP4:具有可定制数据平面的应用感知网络架构","authors":"Ouassim Karrakchou, N. Samaan, A. Karmouch","doi":"10.1109/HPSR52026.2021.9481828","DOIUrl":null,"url":null,"abstract":"Fast and customizable programmable data planes (PDPs) implementing new services such as multi-flow synchronization, on- and in-time delivery, and in-network caching and compression are key enablers to future applications (e.g., streamed holograms, telesurgery, and autonomous industrial systems). This paper outlines the design principles of EP4, an application-aware extended P4-based network architecture that offers hosted applications an extensible catalog of services through its control plane. The latter configures a PDP that can achieve minimal parsing and processing for fast-tracked packets as well as customized processing and forwarding for other packets. An extended parser (eParser) performs the first task, which reduces the necessary latency experienced by packets. Alternatively, adaptive processing is achieved using an enhanced processor (eProcessor) that optionally parses customized headers using just-in-time programmable parsers. It then executes selected P4 packet processing pipelines implementing different services. These programs are installed at runtime without impacting other switch functionalities. Experimental results demonstrate the architecture’s enhanced performance compared to current solutions.","PeriodicalId":158580,"journal":{"name":"2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"EP4: An Application-Aware Network Architecture with a Customizable Data Plane\",\"authors\":\"Ouassim Karrakchou, N. Samaan, A. Karmouch\",\"doi\":\"10.1109/HPSR52026.2021.9481828\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fast and customizable programmable data planes (PDPs) implementing new services such as multi-flow synchronization, on- and in-time delivery, and in-network caching and compression are key enablers to future applications (e.g., streamed holograms, telesurgery, and autonomous industrial systems). This paper outlines the design principles of EP4, an application-aware extended P4-based network architecture that offers hosted applications an extensible catalog of services through its control plane. The latter configures a PDP that can achieve minimal parsing and processing for fast-tracked packets as well as customized processing and forwarding for other packets. An extended parser (eParser) performs the first task, which reduces the necessary latency experienced by packets. Alternatively, adaptive processing is achieved using an enhanced processor (eProcessor) that optionally parses customized headers using just-in-time programmable parsers. It then executes selected P4 packet processing pipelines implementing different services. These programs are installed at runtime without impacting other switch functionalities. Experimental results demonstrate the architecture’s enhanced performance compared to current solutions.\",\"PeriodicalId\":158580,\"journal\":{\"name\":\"2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPSR52026.2021.9481828\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR52026.2021.9481828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
EP4: An Application-Aware Network Architecture with a Customizable Data Plane
Fast and customizable programmable data planes (PDPs) implementing new services such as multi-flow synchronization, on- and in-time delivery, and in-network caching and compression are key enablers to future applications (e.g., streamed holograms, telesurgery, and autonomous industrial systems). This paper outlines the design principles of EP4, an application-aware extended P4-based network architecture that offers hosted applications an extensible catalog of services through its control plane. The latter configures a PDP that can achieve minimal parsing and processing for fast-tracked packets as well as customized processing and forwarding for other packets. An extended parser (eParser) performs the first task, which reduces the necessary latency experienced by packets. Alternatively, adaptive processing is achieved using an enhanced processor (eProcessor) that optionally parses customized headers using just-in-time programmable parsers. It then executes selected P4 packet processing pipelines implementing different services. These programs are installed at runtime without impacting other switch functionalities. Experimental results demonstrate the architecture’s enhanced performance compared to current solutions.