An optimized design approach for 8-bit pipelined ADC using high gain amplifier

Demand of high-performance converters with integrated circuits with combined features and specifications of power consumption, resolution and speed have become very dominant in many emerging applications. Pipelined ADC mixed signal system consists of Sample and Hold, Flash ADC, DAC and Gain amplifier in all the stages. In the present work, a pipeline ADC architecture has 3-stages, with each stage of 3-bits with 3-bit flash ADC followed by a 3-bit binary weighted DAC at each stage. A novel approach to design a 8-bit ADC is implemented, and this design offers less number of comparators compared to flash ADC with less circuit complexity, and 8-bit ADC is designed with improvement in resolution. It is simulated first in MATLAB, but applying 1.8Volts sinusoidal and sampling time of 40 MSPS and clock frequency 10MHz the individual blocks are implemented in LT-spice 180 nm technology with bandwidth of 40 MHz. Then a high gain amplifier is implemented by using Diode connected load differential amplifier with 10mv input voltage and 18Mhz input frequency.