{"title":"3.68aFrms分辨率183dB FoMs四阶连续带通∆Σ 0.18µm CMOS电容-数字转换器","authors":"Sujin Park, Hyungil Chae, Seonghwan Cho","doi":"10.23919/VLSICircuits52068.2021.9492366","DOIUrl":null,"url":null,"abstract":"This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) ∆Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP ∆Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 3.68aFrms Resolution 183dB FoMs 4th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS\",\"authors\":\"Sujin Park, Hyungil Chae, Seonghwan Cho\",\"doi\":\"10.23919/VLSICircuits52068.2021.9492366\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) ∆Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP ∆Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs.\",\"PeriodicalId\":106356,\"journal\":{\"name\":\"2021 Symposium on VLSI Circuits\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSICircuits52068.2021.9492366\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSICircuits52068.2021.9492366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.68aFrms Resolution 183dB FoMs 4th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS
This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) ∆Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP ∆Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs.
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