{"title":"一种改进的单相非对称少器件数多电平逆变器","authors":"S. Malathy, R. Ramaprabha","doi":"10.1109/icesip46348.2019.8938281","DOIUrl":null,"url":null,"abstract":"This paper proposes a new single phase multilevel inverter structure based on an improved fundamental module that utilizes two dc voltage sources and five switches. The functioning of the fundamental module in both symmetric and asymmetric modes is explained in detail. The generalized structure based on the proposed fundamental module and the equations employed to find out the magnitudes of the dc sources are also derived. Nine level and forty nine level inverters are developed and the proposed structures are validated adequately through simulations. The metrics of the proposed reduced device count structure is compared with that of the recently proposed similar structure with regard to the amount of switches, sources and level to switch ratio to demonstrate the precedence of the proposed structure.","PeriodicalId":218069,"journal":{"name":"2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Improved Single Phase Asymmetric Reduced Device Count Multilevel Inverter\",\"authors\":\"S. Malathy, R. Ramaprabha\",\"doi\":\"10.1109/icesip46348.2019.8938281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a new single phase multilevel inverter structure based on an improved fundamental module that utilizes two dc voltage sources and five switches. The functioning of the fundamental module in both symmetric and asymmetric modes is explained in detail. The generalized structure based on the proposed fundamental module and the equations employed to find out the magnitudes of the dc sources are also derived. Nine level and forty nine level inverters are developed and the proposed structures are validated adequately through simulations. The metrics of the proposed reduced device count structure is compared with that of the recently proposed similar structure with regard to the amount of switches, sources and level to switch ratio to demonstrate the precedence of the proposed structure.\",\"PeriodicalId\":218069,\"journal\":{\"name\":\"2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icesip46348.2019.8938281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icesip46348.2019.8938281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Improved Single Phase Asymmetric Reduced Device Count Multilevel Inverter
This paper proposes a new single phase multilevel inverter structure based on an improved fundamental module that utilizes two dc voltage sources and five switches. The functioning of the fundamental module in both symmetric and asymmetric modes is explained in detail. The generalized structure based on the proposed fundamental module and the equations employed to find out the magnitudes of the dc sources are also derived. Nine level and forty nine level inverters are developed and the proposed structures are validated adequately through simulations. The metrics of the proposed reduced device count structure is compared with that of the recently proposed similar structure with regard to the amount of switches, sources and level to switch ratio to demonstrate the precedence of the proposed structure.