D. Lee, F. Tsui, Jeng-Wei Yang, F. Gao, Wen-Juei Lu, Yeeheng Lee, Chi-Tsai Chen, V. Huang, Pin-Yao Wang, M. Liu, H. Hsu, S. Chang, S.Y. Chang, H. van Tran, J. Frayer, Yaw-Wen Hu, B. Yeh, B. Chen
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Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node
We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.
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