采用数字前景校准技术的2GSPS 8位ADC

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2011-06-24 DOI:10.1109/ASID.2011.5967436

Z. Zhang, Yong-lu Wang, Xinlei Huang

{"title":"采用数字前景校准技术的2GSPS 8位ADC","authors":"Z. Zhang, Yong-lu Wang, Xinlei Huang","doi":"10.1109/ASID.2011.5967436","DOIUrl":null,"url":null,"abstract":"A high-speed 8-bit analog-to-digital converter in 0.35µm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating architecture and the dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2GSPS. In case of digital calibration, as a result of testing, the ADC achieves 7.32ENOB at analog input of 484MHz, and 7.1ENOB at Nyquist input after the chip is self-corrected.","PeriodicalId":328792,"journal":{"name":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 2GSPS 8-bit ADC with digital foreground calibration technology\",\"authors\":\"Z. Zhang, Yong-lu Wang, Xinlei Huang\",\"doi\":\"10.1109/ASID.2011.5967436\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-speed 8-bit analog-to-digital converter in 0.35µm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating architecture and the dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2GSPS. In case of digital calibration, as a result of testing, the ADC achieves 7.32ENOB at analog input of 484MHz, and 7.1ENOB at Nyquist input after the chip is self-corrected.\",\"PeriodicalId\":328792,\"journal\":{\"name\":\"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASID.2011.5967436\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASID.2011.5967436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

提出了一种采用0.35µm BiCMOS工艺的高速8位模数转换器。该ADC采用独特的折叠插值架构和双通道定时交错复用技术，实现2GSPS的采样率。在数字校准的情况下，经过测试，ADC在484MHz的模拟输入达到7.32ENOB，在芯片自我校正后，在Nyquist输入达到7.1ENOB。

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A 2GSPS 8-bit ADC with digital foreground calibration technology

A high-speed 8-bit analog-to-digital converter in 0.35µm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating architecture and the dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2GSPS. In case of digital calibration, as a result of testing, the ADC achieves 7.32ENOB at analog input of 484MHz, and 7.1ENOB at Nyquist input after the chip is self-corrected.

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来源期刊

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification

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