H. Barringer, G. Gough, Brian Monahan, A. Williams, M. Arcus, A. Armstrong, M. Hill
{"title":"ELLA的设计和验证环境","authors":"H. Barringer, G. Gough, Brian Monahan, A. Williams, M. Arcus, A. Armstrong, M. Hill","doi":"10.1109/ASPDAC.1995.486387","DOIUrl":null,"url":null,"abstract":"We describe a fully integrated design environment for the Hardware Description Language ELLA, which provides formal verification support to the hardware engineer. The environment includes both conventional hardware design tools, and special purpose tools for ELLA-level design transformation, symbolic simulation and formal verification. All tools operate from an underlying formal semantic representation of ELLA. The operation of the various tools is described from the user viewpoint via a simple design example.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A design and verification environment for ELLA\",\"authors\":\"H. Barringer, G. Gough, Brian Monahan, A. Williams, M. Arcus, A. Armstrong, M. Hill\",\"doi\":\"10.1109/ASPDAC.1995.486387\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a fully integrated design environment for the Hardware Description Language ELLA, which provides formal verification support to the hardware engineer. The environment includes both conventional hardware design tools, and special purpose tools for ELLA-level design transformation, symbolic simulation and formal verification. All tools operate from an underlying formal semantic representation of ELLA. The operation of the various tools is described from the user viewpoint via a simple design example.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486387\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486387","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We describe a fully integrated design environment for the Hardware Description Language ELLA, which provides formal verification support to the hardware engineer. The environment includes both conventional hardware design tools, and special purpose tools for ELLA-level design transformation, symbolic simulation and formal verification. All tools operate from an underlying formal semantic representation of ELLA. The operation of the various tools is described from the user viewpoint via a simple design example.
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