180nm CMOS高线性高隔离背闸效应SPDT开关IC及浮体技术

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377902

Xiao Xu, Xin Yang, Zheng Sun, T. Kurniawan, T. Yoshimasu

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引用次数: 4

摘要

提出了一种180纳米CMOS制程的宽带单极双掷(SPDT)开关IC。采用后栅电压注入和浮体技术，同时提高了电源处理能力、插入损耗和隔离性能。在工作频率为5.0 GHz的发射模式下，SPDT开关IC的输入参考0.3 dB压缩点为21.0 dBm，隔离度为42.7 dB，插入损耗为1.1 dB。

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Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

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2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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