A Fast and Efficient Fault Tree Analysis Using Approximate Computing

Fault tree analysis is one of the most widely used methods in reliability calculation and failure probability analysis. Although fault tree analysis is a popular method, its simulation is time-consuming. Therefore, speeding up fault tree simulations is essential for designers to calculate reliability. Several studies that reduced the mentioned simulation time just considered run-time and accuracy as effective parameters; however, power consumption and area efficiency are key parameters in most of the analyses. In this paper, we present a new method which utilizes approximate computing to mitigate the fault tree analysis simulation time, while considering accuracy, area efficiency, and power consumption as effective parameters. This method is capable of analyzing not only static fault trees but also dynamic fault trees. To do so, first, we describe a fault tree model by hardware description language (VHDL), then substitute its time-consuming arithmetic components including adders and multipliers with fast approximate hardware and eventually measure its reliability through Monte Carlo simulation. Experimental results reveal that compared to the best-related works, on average, we have decreased the emulation time by 15.2% and improved power consumption and circuit area by 61.9%, 68.8%, respectively with negligible inaccuracy.