MOS models for LIM transient simulations

This paper presents an approach for the transient simulation of circuits through the latency insertion model using advanced models for MOS transistors. By taking into account the dynamic charge storage effects in short-channel devices a more accurate simulation of high-speed digital and analog circuits via the latency insertion method can be performed. The approach makes use of the SPICE LEVEL 3 transistor model for MOSFETs. In addition the use of the latency insertion method allows better convergence and higher computational speed for the simulation. Several computer simulations are performed to validate the method. Results show improvement in accuracy by using the high-level models.