Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI- MOSFETs: A TCAD Investigation

Using TCAD simulations, we have identified the existence of a sub-surface conducting region, below the Si/SiO2 interface, with significant electron concentration, in short channel bulk MOSFETs (p-type silicon substrate), at high accumulation bias. This is symptomatic of weakening gate control. The electron concentration in this sub-surface region is shown to be dependent on oxide thickness, channel length and source-drain junction depth. In the case of short channel nanoscale Double Gate SOI (DGSOI) MOSFETs, studied for different SOI channel thicknesses, despite quantum confinement effects, the electron concentration is found to be considerably reduced at lower SOI channel thicknesses, compared to Bulk MOSFETs.