ISO 8802-2.2协议的并行实现

Proceedings of TRICOMM `91: IEEE Conference on Communications Software: Communications for Distributed Applications and Systems Pub Date : 1991-04-18 DOI:10.1109/TRICOM.1991.152878

M. Kaiserswerth

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引用次数: 9

摘要

描述了基于多处理器的通信适配器上ISO 8802-2.2逻辑链路控制协议的并行实现。详细的测量允许作者构造和参数化实现的模型。该模型显示了不同协议功能的流水线化是可能的，以及在不同的处理器配置上运行实现时预期的性能增益。并行实现的性能超过每秒16000个信息协议数据单位，与100 Mb/s范围内运行的新兴高速网络相当。

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A parallel implementation of the ISO 8802-2.2 protocol

A parallel implementation of the ISO 8802-2.2 Logical Link Control protocol on a multiprocessor-based communication adapter is described. Detailed measurements allow the authors to construct and parameterize a model of the implementation. The model shows how pipelining of different protocol functions is possible and what performance gain can be expected when running the implementation on different processor configurations. The performance of the parallel implementation is more than 16000 information protocol data units per second, commensurate with emerging high-speed networks operating in the 100 Mb/s range.<>

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Proceedings of TRICOMM `91: IEEE Conference on Communications Software: Communications for Distributed Applications and Systems

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