一种55纳米逻辑工艺兼容的分闸闪存阵列，在汽车温度下具有高存取速度和可靠性

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI:10.1109/IMW.2015.7150267

N. Do, L. Tee, S. Hariharan, S. Lemke, M. Tadayoni, W. Yang, M. Wu, JinHo Kim, Yueh-Hsin Chen, C. Su, V. Tiwari, Stephen Zhou, R. Qian, I. Yue

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引用次数: 8

摘要

在本文中，采用高密度分栅(SG) SuperFlash®单元阵列设计的Flash宏，兼容地嵌入到55 nm低功耗(LP)逻辑工艺中，在汽车温度范围内具有完整的功能和出色的可靠性。这种分栅闪存技术可以无缝地、普遍地嵌入到多种逻辑处理平台中，并且可以不断地扩展到40纳米和更小的光刻节点，而不会影响性能和可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

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来源期刊

2015 IEEE International Memory Workshop (IMW)

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