Low power conventional universal shift register using 4: 1 multiplexer

A shift register consists of a chain of flip-flops in cascade, with the output of one flip-flop connected. Flip-flop consumes power and constitute load on the clock distribution. To achieve the high performance in universal shift register, flip-flops play the important role. This paper presents the conventional universal shift register using edge triggered D flip flop with low power and area efficient applications. The D flip-flop is realized using minimum number of transistors hence reducing the manufacturing cost. Microwind simulation results of Universal Shift Register indicate improvement in power-delay product in the range of milliwatt.