{"title":"一个精确的,低阻抗,低差的亚v带隙基准","authors":"Kin Keung Jeff Lau","doi":"10.1109/ISSCS.2013.6651183","DOIUrl":null,"url":null,"abstract":"A compact, accurate sub-1V low impedance, low dropout bandgap reference is presented in this paper. Firstly, a new 1V bandgap core (corel) is introduced by the simple addition of two resistors to the generic core. Using this concept, an improved version (core 2) is presented to generate a sub-1V(0.9V in the design example) bandgap reference that can be set from a bit above Vbe, up to the normal bandgap voltage. Both cores are in low dropout and low output impedance configurations. The circuit idea is realized in 90nm BiCMOS technology. Simulation results show that over a 200oC temperature range, core 1 can achieve 20ppm over line and load regulation. Core 2 can achieve 15ppm over line and load regulation. Both cores can be realized in a CMOS process using parasitic PNP devices.","PeriodicalId":260263,"journal":{"name":"International Symposium on Signals, Circuits and Systems ISSCS2013","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An accurate, low impedance, low dropout sub-V bandgap reference\",\"authors\":\"Kin Keung Jeff Lau\",\"doi\":\"10.1109/ISSCS.2013.6651183\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A compact, accurate sub-1V low impedance, low dropout bandgap reference is presented in this paper. Firstly, a new 1V bandgap core (corel) is introduced by the simple addition of two resistors to the generic core. Using this concept, an improved version (core 2) is presented to generate a sub-1V(0.9V in the design example) bandgap reference that can be set from a bit above Vbe, up to the normal bandgap voltage. Both cores are in low dropout and low output impedance configurations. The circuit idea is realized in 90nm BiCMOS technology. Simulation results show that over a 200oC temperature range, core 1 can achieve 20ppm over line and load regulation. Core 2 can achieve 15ppm over line and load regulation. Both cores can be realized in a CMOS process using parasitic PNP devices.\",\"PeriodicalId\":260263,\"journal\":{\"name\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCS.2013.6651183\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Signals, Circuits and Systems ISSCS2013","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2013.6651183","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An accurate, low impedance, low dropout sub-V bandgap reference
A compact, accurate sub-1V low impedance, low dropout bandgap reference is presented in this paper. Firstly, a new 1V bandgap core (corel) is introduced by the simple addition of two resistors to the generic core. Using this concept, an improved version (core 2) is presented to generate a sub-1V(0.9V in the design example) bandgap reference that can be set from a bit above Vbe, up to the normal bandgap voltage. Both cores are in low dropout and low output impedance configurations. The circuit idea is realized in 90nm BiCMOS technology. Simulation results show that over a 200oC temperature range, core 1 can achieve 20ppm over line and load regulation. Core 2 can achieve 15ppm over line and load regulation. Both cores can be realized in a CMOS process using parasitic PNP devices.