具有8ns串行访问时间的4mbit CMOS SRAM

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111090

H. Kuriyama, T. Hirose, S. Murakami, T. Wada, K. Fujita, Y. Nishimura, K. Anami

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引用次数: 1

摘要

采用新提出的电路(分层移位寄存器和预读电路)，在4mb静态RAM中实现了8ns的串行访问时间，可访问4mb。该存储器实现了125 mhz的快速串行读/写操作，适用于超高速存储系统，如图像处理系统，高速测试系统和超级计算机。此功能也有利于减少RAM的测试时间

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A 4-Mbit CMOS SRAM with 8-ns serial-access time

An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial for reducing the testing time of the RAM

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来源期刊

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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