{"title":"用于QPSK调制的NB-IoT快速锁定双频锁相环","authors":"Jae Hyung Jung, Kangyoon Lee","doi":"10.1109/ICUFN57995.2023.10200692","DOIUrl":null,"url":null,"abstract":"This paper represents PLL (Phase Locked Loop) for dual band communication of NB-IoT and LPWAIoT, of which the Band width is 699MHz to 960MHz, 1710MHz to 2170MHz. The lock time of the PLL improved by combining the digital operation with analog when tracking the target frequency. In the proposed PLL architecture, many techniques are used to fasten lock time, to cover the wide range of the VCO (Voltage Controlled Oscillator) for the QPSK (Quaternary Phase Shift Keying) communication. The proposed PLL is designed with 65nm CMOS technology and covers the operating frequency range from 2624 MHz to 4471 MHz with a reference clock frequency of 30.72 MHz. The measured phase noise performance of the proposed PLL is 106.15 dBc/Hz at a VCO output frequency of 4.34 GHz at an offset frequency of 1MHz.","PeriodicalId":341881,"journal":{"name":"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Fast Locking Dual Band PLL for NB-IoT with QPSK Modulation\",\"authors\":\"Jae Hyung Jung, Kangyoon Lee\",\"doi\":\"10.1109/ICUFN57995.2023.10200692\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper represents PLL (Phase Locked Loop) for dual band communication of NB-IoT and LPWAIoT, of which the Band width is 699MHz to 960MHz, 1710MHz to 2170MHz. The lock time of the PLL improved by combining the digital operation with analog when tracking the target frequency. In the proposed PLL architecture, many techniques are used to fasten lock time, to cover the wide range of the VCO (Voltage Controlled Oscillator) for the QPSK (Quaternary Phase Shift Keying) communication. The proposed PLL is designed with 65nm CMOS technology and covers the operating frequency range from 2624 MHz to 4471 MHz with a reference clock frequency of 30.72 MHz. The measured phase noise performance of the proposed PLL is 106.15 dBc/Hz at a VCO output frequency of 4.34 GHz at an offset frequency of 1MHz.\",\"PeriodicalId\":341881,\"journal\":{\"name\":\"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICUFN57995.2023.10200692\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUFN57995.2023.10200692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast Locking Dual Band PLL for NB-IoT with QPSK Modulation
This paper represents PLL (Phase Locked Loop) for dual band communication of NB-IoT and LPWAIoT, of which the Band width is 699MHz to 960MHz, 1710MHz to 2170MHz. The lock time of the PLL improved by combining the digital operation with analog when tracking the target frequency. In the proposed PLL architecture, many techniques are used to fasten lock time, to cover the wide range of the VCO (Voltage Controlled Oscillator) for the QPSK (Quaternary Phase Shift Keying) communication. The proposed PLL is designed with 65nm CMOS technology and covers the operating frequency range from 2624 MHz to 4471 MHz with a reference clock frequency of 30.72 MHz. The measured phase noise performance of the proposed PLL is 106.15 dBc/Hz at a VCO output frequency of 4.34 GHz at an offset frequency of 1MHz.