一种用于FPGA实现的低面积FIR滤波器

2011 34th International Conference on Telecommunications and Signal Processing (TSP) Pub Date : 2011-10-13 DOI:10.1109/TSP.2011.6043675

C. Damian, E. Lunca

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引用次数: 7

摘要

本文提出了一种用于在现场可编程门阵列(FPGA)器件中实现FIR(有限脉冲响应)滤波器的高速低面积架构。新的FIR滤波器没有乘法块，只使用加法器和移位寄存器。这是可能的，因为执行了系数近似，使用一种算法计算系数，就像计算两项的幂的和一样。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low area FIR filter for FPGA implementation

This paper proposes a high speed and low area architecture for the implementation of a FIR (Finite Impulse Response) filter into a Field Programmable Gate Array (FPGA) device. The new FIR filter type is implemented with no multiplication block, using only adders and shifting registers. This is possible because a coefficient approximation is performed, using an algorithm that computes the coefficients like a sum-of-power-of-two terms.

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2011 34th International Conference on Telecommunications and Signal Processing (TSP)

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