Truncated Wallace Based Single Precision Floating Point Multiplier

Hardware implementation of digital signal processing algorithms such as filters largely requires multipliers. For addressing dynamic range of data to be processed floating point representation are preferred over fixed point. But floating point multiplier imposes challenges to designer due to their significant delay and area. Here, floating point multiplier in round to zero mode is investigated and truncated wallace tree is proposed for mantissa multiplication. Comparison reveals that number of full adders is reduced by 30% and number of half adders is reduced by 39.7% when truncation of binary bits is employed. With the help of Verilog description and Xilinx Vivado design suite existing and proposed structure were implemented targeting Artix-7 FPGA.