{"title":"一种新型65nm LP亚稳态测量测试电路","authors":"S. Beer, R. Ginosar","doi":"10.1109/EEEI.2012.6377044","DOIUrl":null,"url":null,"abstract":"Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown. Measurements are compared to simulations for a fabricated 65nm bulk CMOS circuit build.","PeriodicalId":177385,"journal":{"name":"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A new 65nm LP metastability measurment test circuit\",\"authors\":\"S. Beer, R. Ginosar\",\"doi\":\"10.1109/EEEI.2012.6377044\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown. Measurements are compared to simulations for a fabricated 65nm bulk CMOS circuit build.\",\"PeriodicalId\":177385,\"journal\":{\"name\":\"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EEEI.2012.6377044\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EEEI.2012.6377044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new 65nm LP metastability measurment test circuit
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown. Measurements are compared to simulations for a fabricated 65nm bulk CMOS circuit build.
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