Pragmatic approaches to implement self-checking mechanism in UVM based TestBench

Functional Verification of today's highly complex designs cannot rely simply on static verification techniques as these techniques are incapable of verifying modern complex digital designs. However, Simulation-Based Verification (SBV) which comes under dynamic verification approach can handle these complex systems. Among the various modern SBV approaches, Universal Verification Methodology (UVM) provides well established and flexible solution for complex system design verification. Flexibility of UVM lies in the fact that the verification environment developed using UVM consists of reusable components and is supported by tools of all major vendors of the industry. UVM provides a complete framework to achieve coverage driven verification that includes automatic test generation, self-checking testbenches and coverage metrics [1]. The self-checking capability provided by UVM is not very well defined and, hence, forces verification engineer to develop complex checking mechanism even for very small designs and also provides less resources for thorough checking of complex designs. In this paper, we will discuss implementation details of different kind of checking mechanisms that can be used along with UVM based verification environment to improve its capability of functional checking, protocol checking and reaching hidden bugs of the Design Under Verification (DUV).