用于数字多媒体广播应用的10b 25MS/s 4.8mW 0.13um CMOS ADC

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320892

Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seunghoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon

{"title":"用于数字多媒体广播应用的10b 25MS/s 4.8mW 0.13um CMOS ADC","authors":"Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seunghoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon","doi":"10.1109/CICC.2006.320892","DOIUrl":null,"url":null,"abstract":"A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications\",\"authors\":\"Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seunghoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon\",\"doi\":\"10.1109/CICC.2006.320892\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320892\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

基于低功耗系统应用的开关偏置功耗降低技术，采用0.13 μ m CMOS实现的10b两级流水线ADC以25MS/s和10MS/s的双采样时钟速率工作。该原型ADC在高达25MS/s的所有采样速率下的最大SNDR和SFDR分别为56dB和65dB。ADC的有效芯片面积为0.8mm2，在1.2V电源下，在25MS/s和10MS/s分别消耗4.8mW和2.4mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications

A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Custom Integrated Circuits Conference 2006

自引率

0.00%

发文量