基于可重构硬件的凸包算法硬件加速新方法

Kris Min, Brenda Ly, Joshua Garner, Shahnam Mirzaei
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引用次数: 0

摘要

本文提出了一种基于FPGA的Andrew凸壳单调链软件算法的高速实现方法。最简单形式的凸包是包含一组离散点的最小凸多边形,在工程、数学和科学中有许多应用。假设数据点已排序,凸包算法在最佳情况下具有线性时间复杂度。我们的实现目标是芯片平台上的Zynq系统。我们通过设计可以并行工作的组件来加速软件算法。这包括使用突发传输、动态分支预测和资源共享。我们的方法在100 MHz时钟下实现了4级并行性的2.18速度提升。通过增加并行级别可以获得更高的速度。据我们所知,我们提出的方法是唯一可用的硬件加速实现,真正优化船体处理数据路径。这与其他竞争软件加速形成对比,这些软件加速使用额外的预处理步骤来减少要处理的数据点的数量,或者通过使用高速接口来增加加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware
This paper presents a novel high speed implementation of Andrew's Convex Hull Monotone Chain software algorithm on FPGA. Convex hull in its simplest form is the smallest convex polygon that contains a set of discrete points with many applications in engineering, mathematics and science. Convex hull algorithm in its best case has a linear time complexity assuming data points are sorted. Our implementation targets Zynq system on chip platform. We accelerate the software algorithm by designing components that can work in parallel. This involves using burst transfer, dynamic branch prediction, and resource sharing.. Our approach achieves a speed up of 2.18 for 4 levels of parallelism at 100 MHz clock. Higher speed up can be attained by increasing the levels of parallelism. To the best of our knowledge, our proposed method is the only available hardware accelerated implementation that truly optimizes the hull processing datapath. This is in contrast with other competitive software acceleration which reduce the number of data points to be processed using additional preprocessing steps or increase the speedup by using high speed interface.
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