QFN封装中键合线互连的表征

Q. Xiao
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引用次数: 0

摘要

本文讨论了四平无引线封装中键合线互连的模型和测量方法。以3mm 14引线QFN引线框架与GaAs芯片之间的键合线互连为例,演示了建模和测量过程。测量结果与提取的模型和电磁仿真进行了比较,验证了模型和仿真的准确性。基于提取的简化模型,讨论了键合线互连的理论带宽限制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Characterization of Bond Wire Interconnects in QFN Packages
This paper discusses models and measurements of bond wire interconnects in Quad-Flat No-lead (QFN) packages. A bond wire interconnect between a 3 mm, 14-lead QFN lead frame and a GaAs chip is used as an example to demonstrate the modelling and measurement process. Measurement results are compared with extracted models and electromagnetic (EM) simulations to verify model and simulation accuracy. Based on the extracted simplified model, theoretical bandwidth limitations of bond wire interconnects are discussed.
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