使用可修复逻辑的抗故障8位吠陀乘法器

B. S. Krishna, P. Lakshmi, Sarada Musala
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引用次数: 2

摘要

在数据传输、数据处理等重要应用中频繁使用算术和逻辑单元的当前场景中,精度起着至关重要的作用。因此,抗故障电路已成为近年来研究的课题。这篇论文属于类似的期刊,生产一个使用抗故障逻辑门构建的抗故障8位吠陀乘法器。在任何情况下,该电路的输出都是完全可靠的,因为它避免了最大可能的软故障。在存在故障的情况下,引入修复信号,提供真实的输出。这是以硬件重复为代价实现的,但延迟,即关键路径保持与传统电路相同,没有容错或修复电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fault Resistant 8-Bit Vedic Multiplier Using Repairable Logic
In the present scenario with the high frequency use of arithmetic and logic units in significant applications like data transmission, data processing and many, accuracy plays a crucial role. Hence fault resistant circuits have been recent topic of research. This paper comes under the similar journal producing a fault resistant 8 Bit Vedic Multiplier that is build using fault resistant logic gates. At any case the output of this circuit is completely reliable as it avoids the maximum possible soft faults. In the presence of fault, repair signal is introduced to provide the truthful output. This is achieved at a cost of hardware duplication but the delay i.e the critical path remains same as that of the conventional circuit without fault tolerant or repair circuitry.
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