R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev
{"title":"无线通信标准LDPC解码器体系结构的FPGA实现","authors":"R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev","doi":"10.1109/MOCAST52088.2021.9493380","DOIUrl":null,"url":null,"abstract":"This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards\",\"authors\":\"R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev\",\"doi\":\"10.1109/MOCAST52088.2021.9493380\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.\",\"PeriodicalId\":146990,\"journal\":{\"name\":\"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MOCAST52088.2021.9493380\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST52088.2021.9493380","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards
This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.