一种w波段电流组合功率放大器,Psat为14.8dBm,最大PAE为9.4%

Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang
{"title":"一种w波段电流组合功率放大器,Psat为14.8dBm,最大PAE为9.4%","authors":"Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2011.5940619","DOIUrl":null,"url":null,"abstract":"We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"23 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS\",\"authors\":\"Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang\",\"doi\":\"10.1109/RFIC.2011.5940619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.\",\"PeriodicalId\":448165,\"journal\":{\"name\":\"2011 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"23 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2011.5940619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2011.5940619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26

摘要

我们提出了一种采用双向电流合成器的101-117GHz功率放大器(PA)。它提供高达14.8dBm的饱和输出功率,功率增益超过14dB,功率附加效率(PAE)优于9.4%,也优于11.6dBm的输出P1dB。PA采用三级变压器耦合差分结构,集成输入和输出平衡。为了保证稳定性和提高效率,PA前两级采用级联码结构,最后一级采用共源结构。电流功率合并器用于将来自两个独立pa的功率组合在一起。整个PA芯的芯片面积为0.106 mm2,功耗约200mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS
We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信