一种利用增强型dsp进行图像处理的多处理器系统

[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI:10.1109/ARRAYS.1988.18098

H. Ueda, K. Kato, H. Matsushima, K. Kaneko, M. Ejiri

{"title":"一种利用增强型dsp进行图像处理的多处理器系统","authors":"H. Ueda, K. Kato, H. Matsushima, K. Kaneko, M. Ejiri","doi":"10.1109/ARRAYS.1988.18098","DOIUrl":null,"url":null,"abstract":"A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A multiprocessor system utilizing enhanced DSPs for image processing\",\"authors\":\"H. Ueda, K. Kato, H. Matsushima, K. Kaneko, M. Ejiri\",\"doi\":\"10.1109/ARRAYS.1988.18098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<<ETX>>\",\"PeriodicalId\":339807,\"journal\":{\"name\":\"[1988] Proceedings. International Conference on Systolic Arrays\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] Proceedings. International Conference on Systolic Arrays\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARRAYS.1988.18098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] Proceedings. International Conference on Systolic Arrays","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARRAYS.1988.18098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了一种由64个数字信号处理器(dsp)组成的通用图像处理器(gip)，在0.31 m/sup / box中执行广泛的图像处理任务。为此，专门开发了一种高速DSP，称为DSP-i。它具有高度并行的体系结构，具有两级指令层次结构、多银行缓存和多处理器接口。DSP-i机器周期为50ns。一种新颖的环移位寄存器总线结构为系统提供了灵活的结构和高效的数据交换方法。与四种建议的操作模式一起，它将多处理开销减少到20%。gip的性能为1000mops(每秒百万次操作)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A multiprocessor system utilizing enhanced DSPs for image processing

A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

[1988] Proceedings. International Conference on Systolic Arrays

自引率

0.00%

发文量