{"title":"缺陷检测器的高级合成","authors":"F.S. Verdier, B. Zavidovique","doi":"10.1109/CAMP.1995.521066","DOIUrl":null,"url":null,"abstract":"We present an innovative methodology aimed at rapidly designing image processing systems. Within this environment the first step consists in emulating an IP algorithm on a massively parallel dedicated computer. A compact and functionally equivalent VLSI circuit is then derived by using a high level synthesis system called ALPHA. The whole methodology is presented and illustrated with an IP algorithm effectively designed.","PeriodicalId":277209,"journal":{"name":"Proceedings of Conference on Computer Architectures for Machine Perception","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High level synthesis of a defect detector\",\"authors\":\"F.S. Verdier, B. Zavidovique\",\"doi\":\"10.1109/CAMP.1995.521066\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an innovative methodology aimed at rapidly designing image processing systems. Within this environment the first step consists in emulating an IP algorithm on a massively parallel dedicated computer. A compact and functionally equivalent VLSI circuit is then derived by using a high level synthesis system called ALPHA. The whole methodology is presented and illustrated with an IP algorithm effectively designed.\",\"PeriodicalId\":277209,\"journal\":{\"name\":\"Proceedings of Conference on Computer Architectures for Machine Perception\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Conference on Computer Architectures for Machine Perception\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAMP.1995.521066\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Conference on Computer Architectures for Machine Perception","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAMP.1995.521066","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present an innovative methodology aimed at rapidly designing image processing systems. Within this environment the first step consists in emulating an IP algorithm on a massively parallel dedicated computer. A compact and functionally equivalent VLSI circuit is then derived by using a high level synthesis system called ALPHA. The whole methodology is presented and illustrated with an IP algorithm effectively designed.
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