Programming the CELL-BE using CSP

The current trend in processor design seems to focus on using multiple cores, similar to a cluster-on-a-chip model. These process ors are generally fast and power efficient, but due to their highly parallel nature, the y are notoriously difficult to program for most scientists. One such processor is the CEL L broadband engine (CELL-BE) which is known for its high performance, but also f or a complex programming model which makes it difficult to exploit the architectu re to its full potential. To address this difficulty, this paper proposes to change the programming model to use the principles of CSP design, thus making it simpler to pr ogram the CELL-BE and avoid livelocks, deadlocks and race conditions. The CSP model described here comprises a thread library for the synergistic processing e lem nts (SPEs) and a simple channel based communication interface. To examine the s calability of the implementation, experiments are performed with both scientific c omputational cores and synthetic workloads. The implemented CSP model has a simple API and is shown to scale well for problems with significant computational requ irements.