Parameterized FPGA-based architecture for parallel 1-D filtering algorithms

Parallel 1-D signal filtering algorithm is implemented as a parameterized efficient FPGA-based architecture using Xilinx System Generator. The implemented algorithm is a linear indirect filters achieved by a parallel FFT/point-by-point complex inner product/ IFFT convolution unit array. The implemented architecture manifests a 38 % higher performance per Watt at maximum frequency. The parameterized implementation provides rapid system-level FPGA prototyping and operating frequency portability. Consequently, the results are obtained independent of the two targeted Virtex-6 FPGA boards, namely xc6vlX240Tl–1lff1759 and xc6vlX130Tl–1lff1156, to achieve lower power consumption of (1.6 W) and down to (0.99 W) respectively at a maximum frequency of up to (216 MHz). A case study of real-time speech filtering shows excellent performance results of power consumption down to (0.99W) at maximum frequency of up to (216 MHz).