{"title":"多核处理器的操作系统感知缓存优化技术","authors":"H. Khatoon, S. H. Mirza, Talat Altaf","doi":"10.1109/FIT.2011.26","DOIUrl":null,"url":null,"abstract":"Operating system plays a major role in effective memory management and has a significant impact on the performance of applications. In a Chip Multiprocessor, the on-chip memory hierarchy is an important resource that plays a significant role in determining the overall performance of an application. In addition to a number of hardware optimization techniques that work for all types of applications, some software controlled optimization techniques are also effective for improving the performance of on-chip memory hierarchy. This is so because the software controlled techniques generally have a global view of other concurrently running workloads. A better solution to the memory performance problem is to couple the operating system policies and mechanisms to the hardware techniques for management of on-chip memory hierarchy and its optimizations. This paper gives an overview of all such designs that have coupled the on-chip cache optimization techniques with the operating system mechanisms and policies. More techniques are suggested that would be investigated to predict their effectiveness.","PeriodicalId":101923,"journal":{"name":"2011 Frontiers of Information Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Operating System-Aware Cache Optimization Techniques for Multi Core Processors\",\"authors\":\"H. Khatoon, S. H. Mirza, Talat Altaf\",\"doi\":\"10.1109/FIT.2011.26\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Operating system plays a major role in effective memory management and has a significant impact on the performance of applications. In a Chip Multiprocessor, the on-chip memory hierarchy is an important resource that plays a significant role in determining the overall performance of an application. In addition to a number of hardware optimization techniques that work for all types of applications, some software controlled optimization techniques are also effective for improving the performance of on-chip memory hierarchy. This is so because the software controlled techniques generally have a global view of other concurrently running workloads. A better solution to the memory performance problem is to couple the operating system policies and mechanisms to the hardware techniques for management of on-chip memory hierarchy and its optimizations. This paper gives an overview of all such designs that have coupled the on-chip cache optimization techniques with the operating system mechanisms and policies. More techniques are suggested that would be investigated to predict their effectiveness.\",\"PeriodicalId\":101923,\"journal\":{\"name\":\"2011 Frontiers of Information Technology\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Frontiers of Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FIT.2011.26\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Frontiers of Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FIT.2011.26","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Operating System-Aware Cache Optimization Techniques for Multi Core Processors
Operating system plays a major role in effective memory management and has a significant impact on the performance of applications. In a Chip Multiprocessor, the on-chip memory hierarchy is an important resource that plays a significant role in determining the overall performance of an application. In addition to a number of hardware optimization techniques that work for all types of applications, some software controlled optimization techniques are also effective for improving the performance of on-chip memory hierarchy. This is so because the software controlled techniques generally have a global view of other concurrently running workloads. A better solution to the memory performance problem is to couple the operating system policies and mechanisms to the hardware techniques for management of on-chip memory hierarchy and its optimizations. This paper gives an overview of all such designs that have coupled the on-chip cache optimization techniques with the operating system mechanisms and policies. More techniques are suggested that would be investigated to predict their effectiveness.