A novel current-race fast CMOS circuit

There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing density applications. However, its performance degrades with increasing the fan-in. In this paper, a novel fast CMOS circuit that is based on a current race is presented and compared with the conventional CMOS logic from the points of view of area, power consumption, and average-time delay. The scheme is verified by simulation adopting the 45 nm CMOS technology with Vdd = 1 V and a 25% reduction in the average propagation delay for a six-input NAND gate is achieved.