Design considerations on sliding-block viterbi detectors for high-speed data transmission

We investigate the impact of synchronization and survivor path memory lengths on latency and the error rate of a sliding-block receiver that implements the Viterbi algorithm for high-speed data transmission over dispersive channels. All of the previous work on Viterbi detection has assumed that the synchronization length equals the survivor path memory length. However, we demonstrate that both of these lengths differ significantly from each other in an optimized parallelized high-speed Viterbi detector design which minimizes latency and implementation complexity while achieving the error-rate performance of a Viterbi detector with very long synchronization and survivor path memory lengths. Uncoded four-level pulse-amplitude-modulation (4-PAM) and four-dimensional 5-PAM trellis-coded modulation transmission systems are considered. For these two systems, sliding-block receivers that include a reduced-state Viterbi detector with two sub states and an eight-state Viterbi detector with embedded decision feedback, respectively, are assumed. We conduct a simulation study to provide insights into the various tradeoffs that can be achieved in terms of implementation complexity, latency, and error-rate performance.