一个90 nm 6.5 GHz 256/spl次/ 64b双电源寄存器文件，拆分解码器方案

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221213

S. Hsu, B. Chatterjee, M. Sachdev, A. Alvandpour, R. Krishnamurthy, S. Borkar

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引用次数: 6

摘要

本文描述了一种在1.2 V、90 nm CMOS下，用于6.5 GHz工作的256/spl次/ 64b 2读1写端口静态寄存器文件。读/写选择驱动器和解码器使用0.9 V更低的电源，减少总能量23%。与传统的静态(动态)位线方案相比，本地/全局位线使用具有条件预充的容错分割解码器方案实现65%(90%)高的直流稳健性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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