{"title":"双问题队列流水Java处理器traja——面向开源处理器项目","authors":"Naohiko Shimizut, Makoto Naitot","doi":"10.1109/APASIC.1999.824066","DOIUrl":null,"url":null,"abstract":"In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A dual issue queued pipelined Java processor TRAJA-toward an open source processor project\",\"authors\":\"Naohiko Shimizut, Makoto Naitot\",\"doi\":\"10.1109/APASIC.1999.824066\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824066\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824066","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dual issue queued pipelined Java processor TRAJA-toward an open source processor project
In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.