{"title":"MTAAP简介和委员会","authors":"L. DeRose","doi":"10.1109/IPDPSW.2014.225","DOIUrl":null,"url":null,"abstract":"Multithreading (MT) programming and execution models, as well as Many Integrated Core (MIC) and hybrid programming with accelerated architectures, are now part of the high-end and mainstream computing scene. This trend has been driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures and processors that fit this profile are Cray's XK and XMT, NVIDIA Kepler, Intel Phi, IBM Cyclops, and several SMT processors from IBM (Power7), AMD, or Intel, as well as heterogeneous clusters with accelerators from AMD and NVIDIA. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"MTAAP Introduction and Committees\",\"authors\":\"L. DeRose\",\"doi\":\"10.1109/IPDPSW.2014.225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multithreading (MT) programming and execution models, as well as Many Integrated Core (MIC) and hybrid programming with accelerated architectures, are now part of the high-end and mainstream computing scene. This trend has been driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures and processors that fit this profile are Cray's XK and XMT, NVIDIA Kepler, Intel Phi, IBM Cyclops, and several SMT processors from IBM (Power7), AMD, or Intel, as well as heterogeneous clusters with accelerators from AMD and NVIDIA. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement.\",\"PeriodicalId\":153864,\"journal\":{\"name\":\"2014 IEEE International Parallel & Distributed Processing Symposium Workshops\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Parallel & Distributed Processing Symposium Workshops\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPDPSW.2014.225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPDPSW.2014.225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multithreading (MT) programming and execution models, as well as Many Integrated Core (MIC) and hybrid programming with accelerated architectures, are now part of the high-end and mainstream computing scene. This trend has been driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures and processors that fit this profile are Cray's XK and XMT, NVIDIA Kepler, Intel Phi, IBM Cyclops, and several SMT processors from IBM (Power7), AMD, or Intel, as well as heterogeneous clusters with accelerators from AMD and NVIDIA. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement.