A real time video processing framework for hardware realization of neighborhood operations with FPGAs

In this work we present a real time video processing framework, which can handle high data throughput rates. Contrary to common digital hardware realizations which use several image line long shift register pipelines for direct calculation of 2D neighborhood operations, we suggest an efficient cyclic image line storage structure by using dual port block RAM buffers, which are available in recent FPGAs. Therefore, our approach does not occupy a huge amount of valuable logic resources in the FPGA for shift registers based data storage and achieves a high data throughput by parallel video data processing paths. With this memory structure we realize — already principally proposed in a previous work — a new hardware architecture of the basic morphological image processing operations erosion and dilation as building blocks. With these building blocks, which are hardware occupation and maximum clock frequency efficient, we also implemented the combined morphological operations opening and closing, which are commonly used for image enhancement like noise reduction and object contour smoothing.