{"title":"基于模糊的工业负荷三相双降压半桥有源电力滤波器实时谐波抑制","authors":"Ranjeeta Patel, Ashish Ranjan Dash, A. Panda","doi":"10.1109/ITEC-INDIA.2017.8356951","DOIUrl":null,"url":null,"abstract":"In recent years, a number of industry applications increased with the use of advanced power electronics devices and frequency inverter fed induction motor. This study presents a highly reliable 3-phase dual-buck half-bridge shunt active power filter (DB HB APF) for the elimination of current harmonics produced by these non-linear loads. The dual buck inverter circuit effectually eliminates the undesirable “shoot-through” occurrence ensues in conventional inverter circuit. The fuzzy based id-iq control strategy with adaptive hysteresis has been adopted to generate the reference compensating current. For validation, the proposed topology is implemented in the OPALRT LAB uses OP5142-Spartan 3 FPGA.","PeriodicalId":312418,"journal":{"name":"2017 IEEE Transportation Electrification Conference (ITEC-India)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Real-time harmonic mitigation using fuzzy based 3-phase dual-buck half-bridge active power filter for industrial load\",\"authors\":\"Ranjeeta Patel, Ashish Ranjan Dash, A. Panda\",\"doi\":\"10.1109/ITEC-INDIA.2017.8356951\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In recent years, a number of industry applications increased with the use of advanced power electronics devices and frequency inverter fed induction motor. This study presents a highly reliable 3-phase dual-buck half-bridge shunt active power filter (DB HB APF) for the elimination of current harmonics produced by these non-linear loads. The dual buck inverter circuit effectually eliminates the undesirable “shoot-through” occurrence ensues in conventional inverter circuit. The fuzzy based id-iq control strategy with adaptive hysteresis has been adopted to generate the reference compensating current. For validation, the proposed topology is implemented in the OPALRT LAB uses OP5142-Spartan 3 FPGA.\",\"PeriodicalId\":312418,\"journal\":{\"name\":\"2017 IEEE Transportation Electrification Conference (ITEC-India)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Transportation Electrification Conference (ITEC-India)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITEC-INDIA.2017.8356951\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Transportation Electrification Conference (ITEC-India)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITEC-INDIA.2017.8356951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Real-time harmonic mitigation using fuzzy based 3-phase dual-buck half-bridge active power filter for industrial load
In recent years, a number of industry applications increased with the use of advanced power electronics devices and frequency inverter fed induction motor. This study presents a highly reliable 3-phase dual-buck half-bridge shunt active power filter (DB HB APF) for the elimination of current harmonics produced by these non-linear loads. The dual buck inverter circuit effectually eliminates the undesirable “shoot-through” occurrence ensues in conventional inverter circuit. The fuzzy based id-iq control strategy with adaptive hysteresis has been adopted to generate the reference compensating current. For validation, the proposed topology is implemented in the OPALRT LAB uses OP5142-Spartan 3 FPGA.