用于数字阵列雷达的1-4GHz CM OS接收前端

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377895

Zongming Duan, Xiaolan Tang, Q. Ma, Yuefei Dai, F. Lin

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引用次数: 1

摘要

1-4GHz接收前端采用0.18 μm CMOS技术实现，适用于数字阵列雷达应用。前端由宽带平衡lna、下变频混频器、电压增益控制放大器(VGA)、差单驱动(D-S驱动)、LO驱动和片上温度自适应增益控制电路组成。前端的增益范围为5- 25db，噪声系数为8.5dB，输出P-1dB为5.2 dBm。在-55 ~ +85°C工作温度范围内，1- 4ghz的增益差小于1.2 dB。总功耗为150mw，包括焊盘在内的模具面积为1.2 mm2。

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A 1–4GHz CM OS receive front-end for digital array radars

A 1-4GHz receive front-end is implemented in 0.18 μm CMOS technology for digital array radar applications. The front-end consists of broadband balun-LNA, down-conversion mixer, voltage gain control amplifier (VGA), differential-to-single driver (D-S Driver), LO driver and on chip temperature self-adaptive gain control circuit. The front-end achieves a gain range of 5-25 dB, a noise figure of 8.5dB, and an output P-1dB of 5.2 dBm. The gain difference is less than 1.2 dB within -55 ~ +85°C operating temperature across 1-4 GHz. The total power consumption is 150 mW, and the die area is 1.2 mm2 including pads.

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2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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