系统在封装中嵌入III-V芯片,采用扇形圆片级封装,用于射频应用

A. Garnier, L. Castagné, F. Greco, T. Guillemet, L. Marechal, Mehdy Neffati, R. Franiatte, P. Coudrain, S. Piotrowicz, G. Simon
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引用次数: 4

摘要

本文讨论了将两个III-V芯片组合成一个系统级封装(SiP),用于射频基站收发器应用。第一个芯片由一个高功率放大器(HPA)和一个GaN-on-SiC上的开关组成。第二个是一个低噪声放大器(LNA)和一个基于GaAs的驱动器。这两款芯片都汇集了各自衬底技术的优点,即氮化镓的高射频和高功率性能以及砷化镓的低噪声能力。SiP采用芯片优先面朝下的扇形晶圆级封装(FOWLP)构建。芯片之间的差距低至$\mathrm{100}\ \mu\mathrm{m}$。电气布线由再分配层(RDL)和用于PCB上倒装芯片组装的球来保证。散热必须与PCB相反,以避免过于复杂的PCB设计。它是通过直接接触HPA背面的cu衬垫作为散热器来管理的。这是通过使用激光烧蚀打开成型化合物,随后在SiP背面镀Cu来实现的。SiP的最终尺寸为$\mathrm{4}\times \mathrm{4}\times \mathrm{0}.\mathrm{35}\ \text{mm}^{\mathrm{3}}$,其最终目标是适应28ghz有源天线阵列所施加的网格尺寸。本文讨论了影响FOWLP工艺流程的GaN和GaAs芯片的具体特征:相对于目标$\mathrm{350}\ \mu\mathrm{m}$厚成型化合物的低厚度($\sim \mathrm{100}\ \mu \mathrm{m}$);切屑背面涂有金,不得去除;芯片前端具有相对较高的拓扑结构(几乎$\mathrm{20}\ \mu\mathrm{m}$)。在类似sip的环境下,在30 GHz、40 GHz和60 GHz频段分别测量0.1 dB/mm、0.2 dB/mm和0.4 dB/mm的信号损耗。这些结果在SiP最终测试的预期中是有希望的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
This paper deals with the packaging of two III-V chips combined to form a System-in-Package (SiP) for RF base transceiver station applications. The first die consists of a high-power amplifier (HPA) and a switch made on GaN-on-SiC. The second one features a low-noise amplifier (LNA) and a driver built on GaAs. Both chips bring together the best of each substrate technology, namely high RF and power performances of GaN, and low-noise capability of GaAs. The SiP was built using fan-out wafer-level packaging (FOWLP) in chip-first face-down configuration. The gap between the chips is as low as $\mathrm{100}\ \mu\mathrm{m}$. Electrical routing is secured by redistribution layer (RDL) and balls for flip-chip assembly on the PCB. Thermal dissipation has to be managed opposite to the PCB to avoid a too complex PCB design. It is managed by directly contacting the HPA backside with a Cu-liner acting as a heat spreader. This is achieved by opening the molding compound using laser ablation, and subsequently plating Cu on the SiP backside. The SiP has a final size of $\mathrm{4}\times \mathrm{4}\times \mathrm{0}.\mathrm{35}\ \text{mm}^{\mathrm{3}}$, which eventually aims at fitting into the meshing size imposed by an active antenna array operating at 28 GHz. This paper addresses GaN and GaAs chips specific features which have an impact for the FOWLP process flow: low thickness ($\sim \mathrm{100}\ \mu \mathrm{m}$) relative to the targeted $\mathrm{350}\ \mu\mathrm{m}$-thick molding compound; chips backside coated with Au which shall not be removed; chip frontside with a relatively high topology (almost $\mathrm{20}\ \mu\mathrm{m}$). Signal losses were measured in an SiP-like environment at 0.1 dB/mm, 0.2 dB/mm and 0.4 dB/mm respectively at 30 GHz, 40 GHz and 60 GHz. These results are promising in anticipation of the SiP final testing.
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