Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara
{"title":"三栅极SOI-FinFET闪存的实验研究","authors":"Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara","doi":"10.1109/SOI.2012.6404366","DOIUrl":null,"url":null,"abstract":"It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.","PeriodicalId":306839,"journal":{"name":"2012 IEEE International SOI Conference (SOI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Experimental study of tri-gate SOI-FinFET flash memory\",\"authors\":\"Y. Liu, T. Kamei, T. Matsukawa, K. Endo, S. O'Uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, M. Masahara\",\"doi\":\"10.1109/SOI.2012.6404366\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.\",\"PeriodicalId\":306839,\"journal\":{\"name\":\"2012 IEEE International SOI Conference (SOI)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International SOI Conference (SOI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2012.6404366\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International SOI Conference (SOI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2012.6404366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Experimental study of tri-gate SOI-FinFET flash memory
It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.